Project Overview

Client: JR Spidell

Faculty Advisor: Dr. Philip Jones

Our project aims to develop a proof-of-concept video pipeline for machine computer vision with the capability of supporting a machine learning algorithm to augment video data. Our team will improve upon a previous senior design team’s bare-metal implantation by making the code more accessible via PYNQ (or python for embedded systems) for future developers who do not have extensive knowledge in low level hardware programming and design.

The design will use a MIPI-connected COTS camera module to a display monitor that executes within a Linux operating system using an FPGA board. Incoming MIPI video data will be sent through a custom configured FPGA-based video pipeline and output a live video stream to a display monitor connected via an active mini displayport cable.

The project’s stretch goal is to pass the incoming video stream through a machine learning algorithm that augments the video before being sent to the display monitor.

FPGA: Ultra96-v2 Xilinx Zynq UltraScale+ MPSoC

Test Pattern Generator (TPG) images used for debugging the pipeline

Team Members

Deniz Tazegul

Video Stream to FPGA

Computer Engineer

Liam Janda

VDMA to DDRM

Computer Engineer

Taylor Johnson

DDRM to Display

Electrical Engineer

Ritwesh Kumar

Video Stream to FPGA

Electrical Engineer

492 Bi-Weekly Reports ❯

492 Team Report 1 492 Team Report 2 492 Team Report 3

491 Weekly Reports ❯

491 Team Report 1 491 Team Report 2 491 Team Report 3 491 Team Report 4 491 Team Report 5 491 Team Report 6 491 Team Report 7 491 Team Report 8 491 Team Report 9 491 Team Report 10

Lightning Talk Presentations ❯

Lightning Talk 1 Lightning Talk 2 Lightning Talk 3 Lightning Talk 4 Lightning Talk 5 Lightning Talk 6 Lightning Talk 7

Design Documents ❯

Design Document Design Presentation Block Diagram Block Diagram - Camera to Monitor Block Diagram - TPG to VDMA